Publication Details

Testing PCBs Based on Boundary Scan and EDIF Data Analysis

KOTÁSEK Zdeněk, TOMÍŠEK Petr and ZBOŘIL František. Testing PCBs Based on Boundary Scan and EDIF Data Analysis. In: Proceedings of the DDECS'98. Szczyrk: unknown, 1998, pp. 95-101. ISBN 83-908409-6-0.
Czech title
Testování PCB založené na Boundary scan a EDIF analýze dat
Type
conference paper
Language
english
Authors
Kotásek Zdeněk, Doc. Ing., CSc. (DCSE FEECS BUT)
Tomíšek Petr (FIT BUT)
Zbořil František, Doc. Ing., CSc. (DCSE FEECS BUT)
Keywords

Boundary Scan, PCBs Testing, Xilinx FPGAs, EDIF Data Analysis

Abstract

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis which is an integral part of EDIF data (Electronic Design Interchange Format), revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use, efficient and user friendly software tools.

Published
1998
Pages
95-101
Proceedings
Proceedings of the DDECS'98
Conference
DDECS 1998, Szczyrk, Poland, PL
ISBN
83-908409-6-0
Place
Szczyrk, PL
BibTeX 
@INPROCEEDINGS{FITPUB6599,
   author = "Zden\v{e}k Kot\'{a}sek and Petr Tom\'{i}\v{s}ek and Franti\v{s}ek Zbo\v{r}il",
   title = "Testing PCBs Based on Boundary Scan and EDIF Data Analysis",
   pages = "95--101",
   booktitle = "Proceedings of the DDECS'98",
   year = 1998,
   location = "Szczyrk, PL",
   ISBN = "83-908409-6-0",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6599"
}
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