Publication Details
Partial Scan Methodology in VHDL Environment
Růžička Richard, Ing. (DCSE FEECS BUT)
Zbořil František, Doc. Ing., CSc. (DCSE FEECS BUT)
Partial Scan Methodoly, VHDL
The paper presents a partial scan design methodology suited for pipelined data paths described at the Register Transfer Level. The presented methodology can be used for the selection of registers into the partial scan chain.
The paper presents a partial scan design methodology suited for pipelined data paths described at the Register Transfer Level. It is based on the structure analysis of the circuit under design and the classification of circuit elements. This consists in selecting a set of registers: a) from which the inputs of other registers can be controlled, or b) in which the outputs of other registers can be observed. The methodology can be used for the selection of registers into the partial scan chain.
@INPROCEEDINGS{FITPUB6608,
author = "Zden\v{e}k Kot\'{a}sek and Richard R\r{u}\v{z}i\v{c}ka and Franti\v{s}ek Zbo\v{r}il",
title = "Partial Scan Methodology in VHDL Environment",
pages = "146--151",
booktitle = "CEI'99",
year = 1999,
location = "Her\'{l}any, SK",
ISBN = "80-88922-05-4",
language = "english",
url = "https://www.fit.vut.cz/research/publication/6608"
}