Publication Details
VHDL RT Level Parser/Analyser of a Source Code
VHDL, RT Level, Testability Analysis
During our research activities in the field of testability analysis it was revealed that it is reasonable to perform the algorithms not on the VHDL source file, but rather on "an useable database" which reflects the structure of the circuit under analysis and the diagnostic features of the elements and connections between them. For this purpose an interface between VHDL source text and the software performing the analysis was defined. The paper deals with a special parser/analyser that accepts a subset of the IEEE Standard 1076 Hardware Description Language oriented to description of digital circuits on RT level of modelling. The parser/analyser produces a special database of four mutually depending files that is suitable for testability analysis.
The paper deals with a special compiler from a VHDL source code to a special database of four mutually depending files that is suitable for testability analysis of the described circuit.
@INPROCEEDINGS{FITPUB6612,
author = "Franti\v{s}ek Zbo\v{r}il",
title = "VHDL RT Level Parser/Analyser of a Source Code",
pages = "150--155",
booktitle = "Proceedings of the fourth international scientific conference Electronic Computers \& Informatics'2000",
year = 2000,
location = "Ko\v{s}ice, SK",
publisher = "Faculty of Electrical Engineering and Informatics, University of Technology Ko\v{s}ice",
ISBN = "80-88922-25-9",
language = "english",
url = "https://www.fit.vut.cz/research/publication/6612"
}