Result Details

Automatic Design of Image Operators Using Evolvable Hardware

SEKANINA, L.; DRÁBEK, V. Automatic Design of Image Operators Using Evolvable Hardware. Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. p. 132-139. ISBN: 80-214-2094-4.
Type
conference paper
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D., FIT (FIT)
Drábek Vladimír, doc. Ing., CSc.
Abstract

An original approach to automatic design of image operators is presented in this paper. The proposed solution employs evolvable hardware at simplified functional level and produces image operators (digital circuits), which can compete against traditional designs in terms of quality and implementation cost in Xilinx's chips.

Keywords

evolvable hardware, image operators, evolutionary design, FPGA

URL
Published
2002
Pages
132–139
Proceedings
Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Conference
IEEE Design and Diagnostics of Electronic Circuits and Systems 2002
ISBN
80-214-2094-4
Publisher
Brno University of Technology
Place
Brno
BibTeX 
@inproceedings{BUT9821,
  author="Lukáš {Sekanina} and Vladimír {Drábek}",
  title="Automatic Design of Image Operators Using Evolvable Hardware",
  booktitle="Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop",
  year="2002",
  pages="132--139",
  publisher="Brno University of Technology",
  address="Brno",
  isbn="80-214-2094-4",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs02/ddecs02.pdf"
}
Projects
Formal Approaches in Digital Design Diagnostics - Testable Design Verification, GACR, Standardní projekty, GA102/01/1531, start: 2001-01-01, end: 2003-12-31, completed
Research groups
Evolvable Hardware Research Group (RG EHW)
Supercomputing Technologies Research Group SC@FIT (RG SC@FIT)
Departments
Faculty of Information Technology (FIT)
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