Publication Details
Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture
Multiprocessor SoC, pipeline/farm architecture, performance prediction
Process- and thread-level parallelism is very often exploited in asynchronous processor pipelines for embedded applications, recently on a chip. The paper deals with simulation of pipelines with one or more workers in each pipeline stage. The number of workers can be adjusted to balance execution time of other stages so as to keep efficiency high. Simulation-based prototyping of such pipeline processor farms using Transim tool can account for communication delays, multitasking, data-dependent variations in workload, CPUs with different speeds, etc. Simulation results for a given task divisible to a few subtasks of arbitrary duration are presented as well as a particular example of a power of a matrix.
@INPROCEEDINGS{FITPUB6899, author = "Vladim\'{i}r Kut\'{a}lek and V\'{a}clav Dvo\v{r}\'{a}k", title = "Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture", pages = "296--299", booktitle = "Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop", year = 2002, location = "Brno, CZ", publisher = "Faculty of Information Technology BUT", ISBN = "80-214-2094-4", language = "english", url = "https://www.fit.vut.cz/research/publication/6899" }