A Design Space Exploration Scheme for High-Level Synthesis Systems

High-Level Synthesis, scheduling, Design space exploration

This paper describes a design exploration methodology that includes scheduling, module selection and clock cycle determination. The underlying methodology is constructed from one preliminary step and three main phases that allow improving every phase independently from the others without affecting their results, as well as it allows incorporation of the proposed techniques in any high-level synthesis system. The method starts by resource-constrained scheduling algorithm, which incorporates a local exploration mechanism to explore the design points so that each change in the resource set is considered as one point in the design space, which need to be further explored during the module selection step. Then during the module selection phase, the methodology systematically explores several combinations of hardware resource configurations (modules configuration set) that are satisfying time constraints and reports the optimal set with a minimum design area to the designer. Finally, clock cycle exploration step is guided automatically by the delays of modules of the configuration set.