Publication Details

Testing PCBs Based on Boundary Scan

KOTÁSEK Zdeněk, TUPEC Pavel and URBIŠ Hynek. Testing PCBs Based on Boundary Scan. In: Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003, pp. 119-122. ISBN 80-7099-509-2.
Type
conference paper
Language
english
Authors
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Tupec Pavel, Ing. (DCSY FIT BUT)
Urbiš Hynek, Ing. (DCSY FIT BUT)
Keywords

Boundary Scan, PCB, FPGA

Abstract

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.

Published
2003
Pages
119-122
Proceedings
Proceedings of International Carpathian Control Conference
Conference
International Carpathian Control Conference, Vysoké Tatry, SK
ISBN
80-7099-509-2
Publisher
The University of Technology Košice
Place
Košice, SK
BibTeX 
@INPROCEEDINGS{FITPUB7216,
   author = "Zden\v{e}k Kot\'{a}sek and Pavel Tupec and Hynek Urbi\v{s}",
   title = "Testing PCBs Based on Boundary Scan",
   pages = "119--122",
   booktitle = "Proceedings of International Carpathian Control Conference",
   year = 2003,
   location = "Ko\v{s}ice, SK",
   publisher = "The University of Technology Ko\v{s}ice",
   ISBN = "80-7099-509-2",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7216"
}
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