Publication Details

Testable Design Verification Using Petri Nets

RŮŽIČKA Richard. Testable Design Verification Using Petri Nets. In: Proceedings of Euromicro Symposium on Digital System Design 2003. Los Alamitos, CA: IEEE Computer Society Press, 2003, pp. 304-311. ISBN 0-7695-2003-0.
Czech title
Verifikace testovatelného návrhu s využitím Petriho sítí
Type
conference paper
Language
english
Authors
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY FIT BUT)
Keywords

Testability Analysis, Testability Verification, Petri Nets, I path, RTL Digital Circuits

Abstract

In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.

Published
2003
Pages
304-311
Proceedings
Proceedings of Euromicro Symposium on Digital System Design 2003
Conference
EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools, Belek, TR
ISBN
0-7695-2003-0
Publisher
IEEE Computer Society Press
Place
Los Alamitos, CA, US
BibTeX 
@INPROCEEDINGS{FITPUB7263,
   author = "Richard R\r{u}\v{z}i\v{c}ka",
   title = "Testable Design Verification Using Petri Nets",
   pages = "304--311",
   booktitle = "Proceedings of Euromicro Symposium on Digital System Design 2003",
   year = 2003,
   location = "Los Alamitos, CA, US",
   publisher = "IEEE Computer Society Press",
   ISBN = "0-7695-2003-0",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7263"
}
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