Publication Details

Cache-Based Parallel Particle Rendering Engine

TIŠNOVSKÝ Pavel, HEROUT Adam and ZEMČÍK Pavel. Cache-Based Parallel Particle Rendering Engine. ElectronicsLetters.com, vol. 2003, no. 1, p. 8. ISSN 1213-161X.

Czech title

Paralelní stroj pro zobrazování částicových systémů založený na mechanismech cache

Type

journal article

Language

english

Authors

Tišnovský Pavel, Ing. (DCGM FIT BUT)
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT)
Zemčík Pavel, prof. Dr. Ing. (DCGM FIT BUT)

Keywords

particle, surfel, particle renderer, particle rendering engine, Field Programmable Gate Array - FPGA, Content Addressable Memory - CAM, Digital Signal Processor - DSP, Programmable Switching Matrix - PSM, Configurable Logic Block - CLB, cache, spatial data locality

Abstract

Current hardware graphics rendering engines efficiently process huge amount of triangle data, but are not as suitable when operating on point-based scenes. This paper presents an architectural design for point-based rendering. We are using a previously developed hardware model featuring FPGA, DSP and CAM memory.

Published

2003

Pages

Journal

ElectronicsLetters.com, vol. 2003, no. 1, ISSN 1213-161X

Book

Electronics Letters

BibTeX

@ARTICLE{FITPUB7280,
   author = "Pavel Ti\v{s}novsk\'{y} and Adam Herout and Pavel Zem\v{c}\'{i}k",
   title = "Cache-Based Parallel Particle Rendering Engine",
   pages = 8,
   booktitle = "Electronics Letters",
   journal = "ElectronicsLetters.com",
   volume = 2003,
   number = 1,
   year = 2003,
   ISSN = "1213-161X",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7280"
}