Publication Details

Analýza a zlepšení testovatelnosti RTL číslicového obvodu

STRNADEL Josef. Analýza a zlepšení testovatelnosti RTL číslicového obvodu. In: Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika. Brno: Faculty of Information Technology BUT, 2003, pp. 24-29. ISBN 80-214-2471-0.

English title

Testability analysis and improvements of a RTL digital circuit

Type

conference paper

Language

czech

Authors

Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT)

Keywords

Testability, testability analysis, design for testability, structured design, partial scan, full scan

Abstract

The paper deals with topics, problems and terms which are close to my PhD research and uses them to demonstrate the motivation and goals of my PhD research and thesis. The research is directed to design an efficient RTL testability analysis method and to demonstrate its application in automated DFT process using scan technique.

Published

2003

Pages

24-29

Proceedings

Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika

Conference

Pracovní seminář Počítačové architektury & diagnostika 2003 pro studenty doktorského studia, Zvíkovské Podhradí, CZ

ISBN

80-214-2471-0

Publisher

Faculty of Information Technology BUT

Place

Brno, CZ

BibTeX

@INPROCEEDINGS{FITPUB7298,
   author = "Josef Strnadel",
   title = "Anal\'{y}za a zlep\v{s}en\'{i} testovatelnosti RTL \v{c}\'{i}slicov\'{e}ho obvodu",
   pages = "24--29",
   booktitle = "Sborn\'{i}k p\v{r}\'{i}sp\v{e}vk\r{u} ze semin\'{a}\v{r}e Po\v{c}\'{i}ta\v{c}ov\'{e} Architektury \& Diagnostika",
   year = 2003,
   location = "Brno, CZ",
   publisher = "Faculty of Information Technology BUT",
   ISBN = "80-214-2471-0",
   language = "czech",
   url = "https://www.fit.vut.cz/research/publication/7298"
}