RTL Testability Verification System

This paper discusses register transfer level (RTL) digital circuit design testability verification. Digital circuit design testability verification is used to judge if the digital circuit design, analyzed and eventually modified by method leading to partial scan, is really testable. This is because the method utilizes I-paths, but doesn't take into account dependencies of these I-paths. So there conflicts and deadlocks may appear when these I-paths in the circuit are set up. The RTL digital circuit design testability verification detects this problem. The main goal of this work is to develop and implement software system for automatic testability verification of register transfer level digital circuit design. In the implementation of the system, a C/E Petri Nets approach is used. The input to the system is formal specification of digital circuit design and list of digital circuit design modifications (scan chain), the output from the system is the decision if the circuit is testable or not. If the system is marked as nontestable, the operator intervention to circuit design must be performed in order to make the circuit testable.