Publication Details

Verifikace testovatelnosti návrhu číslicového obvodu

ŠKARVADA, J. Verifikace testovatelnosti návrhu číslicového obvodu. Proceedings of 10th Conference and Competition Student EEICT 2004, Volume 1. Brno: Fakulta elektrotechniky a komunikačních technologií VUT v Brně, 2004. s. 275-277. ISBN: 80-214-2634-9.
English title
RT level digital circuit design testability verification
Type
conference paper
Language
Czech
Authors
Škarvada Jaroslav, Ing., Ph.D.
URL
Keywords

RT level digital circuit design testability verification, testability, I-path, I-mode, register transfer level, partial scan, C/E Petri net, conflicts and deadlocks, reachability of marking, INA

Abstract

The main goal of this work is to develop and implement software system for automatic testabilty verification of Register Transfer (RT) level Digital Circuit Design (DCD). In the implementation of the system, a C/E Petri Nets approach is used. The input to the system is formal specification of DCD and the output from the system is the decision if the DCD is testable or not.

Published
2004
Pages
275–277
Proceedings
Proceedings of 10th Conference and Competition Student EEICT 2004, Volume 1
ISBN
80-214-2634-9
Publisher
Fakulta elektrotechniky a komunikačních technologií VUT v Brně
Place
Brno
BibTeX 
@inproceedings{BUT17560,
  author="Jaroslav {Škarvada}",
  title="Verifikace testovatelnosti návrhu číslicového obvodu",
  booktitle="Proceedings of 10th Conference and Competition Student EEICT 2004, Volume 1",
  year="2004",
  pages="275--277",
  publisher="Fakulta elektrotechniky a komunikačních technologií VUT v Brně",
  address="Brno",
  isbn="80-214-2634-9",
  url="http://www.feec.vutbr.cz/EEICT/2004/sbornik/02-Magisterske_projekty/09-Pocitacove_systemy/06-xskarv02.pdf"
}
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