Publication Details
The Identification of Registers in RTL Structures
Mika Daniel, Ing. (DCSY FIT BUT)
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT)
digital circuit diagnosis, test scheduling, resource selection, register resources, discrete mathematics, graph, relation, Hasse diagram, coverage problem, set minimization, register-transfer level
A highly efficient test schedule can be created for a given digital circuit if a proper test-scheduling algorithm is selected and if the circuit fulfils several criteria that affect the quality of a resulting test schedule significantly and independently on any scheduling algorithm. If a design for testability techniques are applied to the circuit structure, the way in which they are applied have a big impact on those circuit properties. Thus, it is feasible to deal with the relation between application of selected design for testability techniques and the quality of a resulting test schedule in detail. This is a wide research area. Our paper deals with the register selection technique through which a test will be applied. The paper presents a methodology for selecting registers for the test application in such a way that the cardinality of a set of selected registers is minimized and test resources allocated to functional units are shared in a maximum way. Proposed methodology is mathematically described, definitions are clearly illustrated and experimental results together with the future research perspectives are discussed.
@INPROCEEDINGS{FITPUB7618,
author = "Zden\v{e}k Kot\'{a}sek and Daniel Mika and Josef Strnadel",
title = "The Identification of Registers in RTL Structures",
pages = "317--320",
booktitle = "Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004",
series = "Technical Report TR-2004-6",
year = 2004,
location = "Nicosia, CY",
publisher = "Department of Computer Science of University of Cyprus",
ISBN = "3-540-41613",
language = "english",
url = "https://www.fit.vut.cz/research/publication/7618"
}