Publication Details
VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
Testability analysis, data-path, register-transfer level, transparency, I-path concept, virtual port, digraph, test-pattern data-flow digraph, test-response data-flow digraph, graph algorithm, design for testability, scan, benchmark circuit.
The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.
@INPROCEEDINGS{FITPUB7745,
author = "Josef Strnadel",
title = "VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements",
pages = "190--193",
booktitle = "Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
year = 2005,
location = "Sopron, HU",
publisher = "University of West Hungary",
ISBN = "963-9364-48-7",
language = "english",
url = "https://www.fit.vut.cz/research/publication/7745"
}