Publication Details
On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits
Pečenka Tomáš, Ing. (DCSY FIT BUT)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)
Register-transfer level, synthetic benchmark circuit, testability analysis, evolutionary algorithm
Use of benchmark designs has become an important part of a process of designing complex systems. However, existing register-transfer level benchmark suites are not sufficient for evaluation of new architectures and tools; synthetic benchmark circuits are an alternative. In the paper, it is demonstrated how evolutionary techniques can be used to generate synthetic benchmarks covering a wide scale of testability properties. The generation process is driven by a register-transfer level testability analysis method and generated benchmarks are stored in synthesizable VHDL source-code. Results gained by proposed method together with future research trends are discussed at the end of the paper.
@INPROCEEDINGS{FITPUB7867,
author = "Josef Strnadel and Tom\'{a}\v{s} Pe\v{c}enka and Luk\'{a}\v{s} Sekanina",
title = "On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits",
pages = "107--110",
booktitle = "Proceedings of 5th Electronic Circuits and Systems Conference",
year = 2005,
location = "Bratislava, SK",
publisher = "Slovak University of Technology in Bratislava",
language = "english",
url = "https://www.fit.vut.cz/research/publication/7867"
}