Publication Details
High-level Modelling, Analysis, and Verification on FPGA-based Hardware Design
Smrčka Aleš, Ing., Ph.D. (DITS FIT BUT)
Vojnar Tomáš, prof. Ing., Ph.D. (DITS FIT BUT)
hardware verification, timed systems, high-level modelling, formal analysis
Implementation of network components in hardware is a trend in advanced high-speed network technologies. Incoming packets can be analysed in fast programmable cards using FPGA. Designing such a system is not easy and requires a detailed analysis. In this paper, we discuss analysis and verification of a non-trivial system-the network monitor and analyser Scampi that has been developed within the Liberouter project. The Scampi analyser is implemented in FPGA on a special add-on card. It analyses packets incoming with the speed of several Gbps. We created an abstract model of the design and verified several safety properties. Our main task was to check if there is a risk of
buffer overflow and how to set the length of buffers to prevent
this. First, we made a timed analysis by hand and then we used automated tools - model-checkers Uppaal and TReX. In the following text, we show how to model such a complex system and some results of our analysis and verification. We also propose a framework for modelling and analysis of systems where the throughput of requests, their speed, and the length of buffers are important. The proposed models can be reused when verifying and analysing of systems of the given kind.
@TECHREPORT{FITPUB7969,
author = "Petr Matou\v{s}ek and Ale\v{s} Smr\v{c}ka and Tom\'{a}\v{s} Vojnar",
title = "High-level Modelling, Analysis, and Verification on FPGA-based Hardware Design",
pages = 17,
year = 2005,
location = "Brno, CZ",
publisher = "CESNET National Research and Education Network",
language = "english",
url = "https://www.fit.vut.cz/research/publication/7969"
}