Result Details

High-level Modeling, Analysis and Verification of Programmable Hardware Design

SMRČKA, A. High-level Modeling, Analysis and Verification of Programmable Hardware Design. Proceedings of the Junior Scientist Conference 2006. Vienna: Technical University Wien, 2006. p. 93-94. ISBN: 3-902463-05-8.
Type
abstract
Language
English
Authors
Smrčka Aleš, Ing., Ph.D., DITS (FIT)
Abstract

This work presents an abstract model of the design and verification ofseveral safety properties. The main task was to check if there is arisk of buffer overflow and how to set the length of buffers to preventthis. This work shows how to model such acomplex system by hand and particular results of analysis andverification is also presented.

Keywords

formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis

Published
2006
Pages
93–94
Book
Proceedings of the Junior Scientist Conference 2006
Conference
Junior Scientist Conference 2006
ISBN
3-902463-05-8
Publisher
Technical University Wien
Place
Vienna
BibTeX 
@misc{BUT60508,
  author="Aleš {Smrčka}",
  title="High-level Modeling, Analysis and Verification of Programmable Hardware Design",
  booktitle="Proceedings of the Junior Scientist Conference 2006",
  year="2006",
  pages="93--94",
  publisher="Technical University Wien",
  address="Vienna",
  isbn="3-902463-05-8",
  note="Abstract"
}
Projects
Optická síť národního výzkumu a její nové aplikace, MŠMT, Výzkumná centra (2000-2004), MSM6383917201, start: 2004-01-01, end: 2010-12-31, completed
Research groups
Automated Analysis and Verification Research Group - VeriFIT (RG VERIFIT)
Departments
Department of Intelligent Systems (DITS)
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