Publication Details
Using Petri Nets for RT Level Digital Systems Test Scheduling
Digital circuit, C/E Petri Net, test scheduling, I-paths, structural conflicts
The paper deals with test scheduling for digital systems. Approach with C/E Petri nets is presented and formal model of digital system under test is introduced. Main purpose of this model is identification of structural conflicts and dead locks that may occur during test application phase. The digital system is analyzed on register transfer (RT) level. The obtained results can be used for digital system design partitioning. In this step individual blocks of logic are identified. Finally concurrent test for non-conflicting blocks of logic is scheduled. The advantage of this approach is, that with partitioned circuit, it is possible to view digital circuit design as system on chip (SOC) design and use existing test scheduling methods for SOC.
@INPROCEEDINGS{FITPUB8041,
author = "Jaroslav \v{S}karvada and Richard R\r{u}\v{z}i\v{c}ka",
title = "Using Petri Nets for RT Level Digital Systems Test Scheduling",
pages = "79--86",
booktitle = "Proceedings of 1st International Workshop on Formal Models (WFM'06)",
year = 2006,
location = "Ostrava, CZ",
ISBN = "80-86840-20-4",
language = "english",
url = "https://www.fit.vut.cz/research/publication/8041"
}