Publication Details

On Distribution of Testability Values in Scan-Layout State-Space

STRNADEL Josef. On Distribution of Testability Values in Scan-Layout State-Space. In: Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006, pp. 308-313. ISBN 80-8073-598-0.
Czech title
Rozložení hodnot testovatelnosti ve stavovém prostoru konfigurací scan řetězů
Type
conference paper
Language
english
Authors
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT)
Keywords

digital circuit diagnostics, register-transfer level, circuit data-path, testability analysis, design for testability, testability improvements, scan technique

Abstract

In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greater number of multiple scan-chains within particular scan-layout,
the better testability properties correspond to the scan-layout.

Published
2006
Pages
308-313
Proceedings
Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics
Conference
7TH International Scientific Conference Electronic Computers and Informatics 2006, Herľany, SK
ISBN
80-8073-598-0
Publisher
The University of Technology Košice
Place
Košice, SK
BibTeX 
@INPROCEEDINGS{FITPUB8181,
   author = "Josef Strnadel",
   title = "On Distribution of Testability Values in Scan-Layout State-Space",
   pages = "308--313",
   booktitle = "Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics",
   year = 2006,
   location = "Ko\v{s}ice, SK",
   publisher = "The University of Technology Ko\v{s}ice",
   ISBN = "80-8073-598-0",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8181"
}
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