Publication Details

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

STRNADEL Josef. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics, vol. 25, no. 5, 2006, pp. 441-464. ISSN 1335-9150.
Czech title
Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů
Type
journal article
Language
english
Authors
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT)
URL
Keywords

digital circuit, testing, register-transfer level, data-path, testability analysis, design for testability, scan technique

Abstract

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits.
It is shown if each module stored in a design library is equipped both with information related to design
and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method.
In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose.
Experimental results gained by the method are presented
and compared with results of existing methods.

Published
2006
Pages
441-464
Journal
Computing and Informatics, vol. 25, no. 5, ISSN 1335-9150
Publisher
Slovak Academic Press
BibTeX 
@ARTICLE{FITPUB8201,
   author = "Josef Strnadel",
   title = "Testability Analysis and Improvements of Register-Transfer Level Digital Circuits",
   pages = "441--464",
   journal = "Computing and Informatics",
   volume = 25,
   number = 5,
   year = 2006,
   ISSN = "1335-9150",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8201"
}
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