Detail výsledku

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

STRNADEL, J. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. COMPUTING AND INFORMATICS, 2006, vol. 25, no. 5, p. 441-464. ISSN: 1335-9150.
Typ
článek v časopise
Jazyk
anglicky
Autoři
Strnadel Josef, Ing., Ph.D., UPSY (FIT)
Abstrakt

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits.
It is shown if each module stored in a design library is equipped both with information related to design
and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method.
In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose.
Experimental results gained by the method are presented
and compared with results of existing methods.

Klíčová slova

digital circuit, testing, register-transfer level, data-path, testability analysis, design for testability, scan technique

URL
Rok
2006
Strany
441–464
Časopis
COMPUTING AND INFORMATICS, roč. 25, č. 5, ISSN 1335-9150
BibTeX 
@article{BUT45082,
  author="Josef {Strnadel}",
  title="Testability Analysis and Improvements of Register-Transfer Level Digital Circuits",
  journal="COMPUTING AND INFORMATICS",
  year="2006",
  volume="25",
  number="5",
  pages="441--464",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/8201/"
}
Soubory
Projekty
Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
Optimalizační postupy v diagnostice číslicových systémů, GAČR, Postdoktorandské granty, GP102/05/P193, zahájení: 2005-01-01, ukončení: 2007-12-31, ukončen
Výzkumné skupiny
Výzkumná skupina Spolehlivé číslicové systémy (VZ DEPSYS)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru