Publication Details

I-path Scheduling Algorithm for RT Level Circuits

PEČENKA Tomáš and KOTÁSEK Zdeněk. I-path Scheduling Algorithm for RT Level Circuits. In: MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov, 2006, pp. 174-181. ISBN 80-214-3287-X.
Czech title
Algoritmus plánování I-cest v obvodu na úrovni RT
Type
conference paper
Language
english
Authors
Pečenka Tomáš, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Keywords

i-path, scheduling, backtracking

Abstract

In the paper, a new approach for scheduling i-paths in Register Transfer (RT) level circuits is presented. The proposed algorithm is able to schedule i-paths not only in circuit structure, but also in time. At the beginning, the formal model for modelling data-path of structurally described RT level circuits is defined. This model is then used to define the i-path concept. The main part of the paper is devoted to introduce a method for i-path scheduling. The method is able to monitor component utilization in time and it is able to detect and solve conflicts between i-paths.

Published
2006
Pages
174-181
Proceedings
MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Conference
2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science -- MEMICS'06, Mikulov, CZ
ISBN
80-214-3287-X
Place
Mikulov, CZ
BibTeX 
@INPROCEEDINGS{FITPUB8220,
   author = "Tom\'{a}\v{s} Pe\v{c}enka and Zden\v{e}k Kot\'{a}sek",
   title = "I-path Scheduling Algorithm for RT Level Circuits",
   pages = "174--181",
   booktitle = "MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
   year = 2006,
   location = "Mikulov, CZ",
   ISBN = "80-214-3287-X",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8220"
}
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