Publication Details

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA Lukáš. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007, pp. 243-246. ISBN 1424411610.

Czech title

Type

conference paper

Language

english

Authors

Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)

URL

http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf PDF

Keywords

digital circuit, polymorphic gate, adder, testing

Abstract

TBD

Published

2007

Pages

243-246

Proceedings

2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Conference

The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, PL

ISBN

1424411610

Publisher

IEEE Computer Society

Place

Gliwice, PL

BibTeX

@INPROCEEDINGS{FITPUB8310,
   author = "Luk\'{a}\v{s} Sekanina",
   title = "Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
   pages = "243--246",
   booktitle = "2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
   year = 2007,
   location = "Gliwice, PL",
   publisher = "IEEE Computer Society",
   ISBN = "1424411610",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8310"
}