Publication Details
Space-Time Trade-offs in SW Evaluation of Boolean Functions
Multiple-output Boolean functions, fast sw evaluation, PLA emulation, linked tables, LUT cascades
Fast evaluation of multiple-output Boolean functions with the smallest memory footprint is often required in embedded systems. The paper describes a novel method of linked tables for representation and evaluation of Boolean functions and compares it with traditional methods; PLAs from the MCS-51 micro-controller are used for comparison. Traditional methods use masks to emulate PLA one way or another. The suggested method of linked tables is based on iterative disjunctive decomposition and leads only to a series of table look-ups. Linked tables are also shown to be equivalent to specific "in-line" decision diagrams. They proved to be most flexible in making trade-offs between performance and memory space. The method of linked tables may be quite useful for embedded microprocessor or microcontroller software as well as for digital system simulation.
@INPROCEEDINGS{FITPUB8329,
author = "V\'{a}clav Dvo\v{r}\'{a}k",
title = "Space-Time Trade-offs in SW Evaluation of Boolean Functions",
pages = 6,
booktitle = "Proceedings of The Second International Conference on Systems",
year = 2007,
location = "New York, US",
publisher = "IEEE Computer Society",
ISBN = "0-7695-2807-4",
language = "english",
url = "https://www.fit.vut.cz/research/publication/8329"
}