Detail publikace

Checker Design for On-line Testing of Xilinx FPGA Communication

STRAKA Martin, TOBOLA Jiří a KOTÁSEK Zdeněk. Checker Design for On-line Testing of Xilinx FPGA Communication. In: The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007, s. 152-160. ISBN 0-7695-2885-6.
Název česky
Checker Design for On-line Testing of Xilinx FPGA Communication
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Straka Martin, Ing., Ph.D. (UPSY FIT VUT)
Tobola Jiří, Ing., MBA (FIT VUT)
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT)
Abstrakt

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

Rok
2007
Strany
152-160
Sborník
The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Konference
The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Rome, IT
ISBN
0-7695-2885-6
Vydavatel
IEEE Computer Society
Místo
Rome, IT
BibTeX 
@INPROCEEDINGS{FITPUB8353,
   author = "Martin Straka and Ji\v{r}\'{i} Tobola and Zden\v{e}k Kot\'{a}sek",
   title = "Checker Design for On-line Testing of Xilinx FPGA Communication",
   pages = "152--160",
   booktitle = "The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
   year = 2007,
   location = "Rome, IT",
   publisher = "IEEE Computer Society",
   ISBN = "0-7695-2885-6",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8353"
}
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