Verifying VHDL Design with Multiple Clocks in SMV

Verifikace návrhu VHDL s více hodinami v SMV

conference paper

english

Smrčka Aleš, Ing., Ph.D. (DITS FIT BUT)
Řehák Vojtěch, doc. RNDr. (FI MUNI)
Vojnar Tomáš, prof. Ing., Ph.D. (DITS FIT BUT)
Šafránek David, doc. Mgr., Ph.D. (FI MUNI)
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT)
Řehák Zdeněk (FI MUNI)

model checking, hardware, VHDL, multiple clocks, SMV

The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, ie. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.

The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, ie. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.

2007

148-164

Lecture Notes in Computer Science, vol. 4346, ISSN 0302-9743

Formal Methods: Applications and Technology

Lecture Notes in Computer Science

FMICS06, Bonn, DE

Springer Verlag

Bonn, DE