Publication Details

Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware

DVOŘÁK Václav. Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware. Journal of Software, vol. 2, no. 5, 2007, pp. 52-63. ISSN 1796-217X.
Czech title
Efektivní evaluace vícevýstupových boolovských funkcí ve vestavěném software nebo firmware
Type
journal article
Language
english
Authors
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT)
Keywords

Embedded software, Boolean function evaluation, Binary Decision Diagrams, LUT cascades   

Abstract

The paper addresses software and firmware implementation of multiple-output Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means of compact representation of a large class of sparse Boolean functions, evaluation of which then reduces to multiple indirect memory accesses. The method is compared to a technique of direct PLA emulation and is illustrated on examples. A specialized micro-engine is proposed for even faster evaluation than is possible with universal microprocessors. The presented method is flexible in making trade-offs between performance and memory footprint and may be useful for embedded applications where the processing speed is not critical. Evaluation may run on various CPUs and DSP cores or slightly faster on FPGA-based micro-programmed controllers.

Published
2007
Pages
52-63
Journal
Journal of Software, vol. 2, no. 5, ISSN 1796-217X
BibTeX 
@ARTICLE{FITPUB8405,
   author = "V\'{a}clav Dvo\v{r}\'{a}k",
   title = "Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware",
   pages = "52--63",
   journal = "Journal of Software",
   volume = 2,
   number = 5,
   year = 2007,
   ISSN = "1796-217X",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8405"
}
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