Publication Details
High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA
Internet packet processing, Embeded processors, Handel-C, FPGA
In this paper, we investigate three different realizations
of the same block from different points of view. The mentioned
different realizations include two realizations with
embedded processors (custom 16-bit RISC processor and
general soft-core processor) and the third realization uses
Handel-C as an example of synthesisable high-level abstraction
languages.
The results show that development time of complete
solution (HW and SW) is approximately the same for the
Handel-C design and the design with soft-core processor;
the development time of the Custom 16-bit RISC processor
is about five times higher. Moreover, the throughput of the
Handel-C design measured in the number of bits processed
in one second is the highest. The obtained frequency and
occupied area of the Handel-C design depends on the complexity
of the used program. However, results are comparable
or even better than results of the embedded processors.
@INPROCEEDINGS{FITPUB8413, author = "Tom\'{a}\v{s} Dedek and Tom\'{a}\v{s} Marek and Tom\'{a}\v{s} Mart\'{i}nek", title = "High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA", pages = "648--651", booktitle = "2007 International Conference on Field Programmable Logic and Applications", year = 2007, location = "Amsterdam, US", publisher = "IEEE Computer Society", ISBN = "1-4244-1060-6", doi = "10.1109/FPL.2007.4380737", language = "english", url = "https://www.fit.vut.cz/research/publication/8413" }