Publication Details
Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů
testability analysis, digital circuit, data path, graph algorithm, diagnostics, hierarchical test, design for testability, testability, transparency, register-transfer level
The work deals with problems related to testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on so-called virtual port conception is utilized to describe the information and proposed testability analysis method. The method is based on the idea of searching two special digraphs, each of them modeling transfers of diagnostic data within circuit data path. It is important that transfers of vectors and responses are modeled separately. At the end of the work, possible applications of the method in practise are outlined together with experimental results gained by the method in several areas related to automation of design for testability process.
@BOOK{FITPUB8570,
author = "Josef Strnadel",
title = "Anal\'{y}za a zlep\v{s}en\'{i} testovatelnosti \v{c}\'{i}slicov\'{y}ch obvod\r{u} na \'{u}rovni meziregistrov\'{y}ch p\v{r}enos\r{u}",
pages = 187,
year = 2008,
location = "Brno, CZ",
publisher = "Faculty of Information Technology BUT",
ISBN = "978-80-214-3599-5",
language = "czech",
url = "https://www.fit.vut.cz/research/publication/8570"
}