Publication Details
On Lookup Table Cascade-Based Realizations of Arbiters
LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits
This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.
@INPROCEEDINGS{FITPUB8635,
author = "Petr Miku\v{s}ek and V\'{a}clav Dvo\v{r}\'{a}k",
title = "On Lookup Table Cascade-Based Realizations of Arbiters",
pages = "795--802",
booktitle = "11th EUROMICRO Conference on Digital System Design DSD 2008",
year = 2008,
location = "Parma, IT",
publisher = "IEEE Computer Society",
ISBN = "978-0-7695-3277-6",
language = "english",
url = "https://www.fit.vut.cz/research/publication/8635"
}