Publication Details
Power Conscious RTL Test Scheduling
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Herrman Tomáš, Ing., Ph.D. (DCSY FIT BUT)
Test scheduling, testable block, power consumption, test vectors reordering, integer linear programming
In the paper, a methodology of power conscious RTL test
scheduling is described. The methodology is based on the
fact that circuit under analysis (CUA) is partitioned into
testable blocks (TB), the information about the partitioning
is the input information for the methodology. TBs are
mapped into AMI platform, for each TB the sequences of
test vectors are then derived, a professional tool is used
for this purpose. The sequences of test vectors are then reordered
with the goal to reduce power consumption during
test application by reducing switching activities. The power
consumption estimation is combined with the implemented
platform which allows to gain more precise results. The
values of TBs power consumption are then used in RTL test
scheduling methodology. The goal is to find test schedule
with lowest test application time and lower power consumption
than the required maximal value.
@INPROCEEDINGS{FITPUB8700,
author = "Jaroslav \v{S}karvada and Zden\v{e}k Kot\'{a}sek and Tom\'{a}\v{s} Herrman",
title = "Power Conscious RTL Test Scheduling",
pages = "721--728",
booktitle = "Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools",
year = 2008,
location = "Los Alamitos, US",
publisher = "IEEE Computer Society",
ISBN = "978-0-7695-3277-6",
language = "english",
url = "https://www.fit.vut.cz/research/publication/8700"
}