Optimalizace testu pro nízký příkon

digital circuit testing, low power consumption, test vectors reordering, scan chain reordering

The paper deals with the test optimization for low power consumption. At first the methodology for power consumption estimation during the test application is presented. The methodology can be used for power consumption estimation in NTC, WNTC, WSA, P and E metrics. The technological library is utilized in the methodology. In next part of the paper, the methodology for test vectors and scan chain reordering is presented. In the methodology all reorderings are performed simultaneously. The genetic algorithm is utilized in the process. The advantage of the methodology is direct binding with realization technology that renders more accurate results in comparison with general methods.