Publication Details

Identifikace testovatelných bloků v obvodu na úrovni RT

HERRMAN Tomáš. Identifikace testovatelných bloků v obvodu na úrovni RT. In: Počítačové architektury a diagnostika 2008. Liberec: Liberec University of Technology, 2008, pp. 25-35. ISBN 978-80-7372-378-1.

English title

Testable Block Identification in RT Level Circuits

Type

conference paper

Language

czech

Authors

Herrman Tomáš, Ing., Ph.D. (DCSY FIT BUT)

Keywords

Testable Block, formal model, testability, scan method, evolutionary algorithm, RT level

Abstract

The formal model of Testable block on RT level is presented in the paper. Principles of identification of Testable block are defined. In the next part the details of implementation of methodology is described. At the end of paper is stated contend of doctoral thesis.

Published

2008

Pages

25-35

Proceedings

Počítačové architektury a diagnostika 2008

Conference

Počítačové architektury a diagnostika 2008, Hejnice, CZ

ISBN

978-80-7372-378-1

Publisher

Liberec University of Technology

Place

Liberec, CZ

BibTeX

@INPROCEEDINGS{FITPUB8812,
   author = "Tom\'{a}\v{s} Herrman",
   title = "Identifikace testovateln\'{y}ch blok\r{u} v obvodu na \'{u}rovni RT",
   pages = "25--35",
   booktitle = "Po\v{c}\'{i}ta\v{c}ov\'{e} architektury a diagnostika 2008",
   year = 2008,
   location = "Liberec, CZ",
   publisher = "Liberec University of Technology",
   ISBN = "978-80-7372-378-1",
   language = "czech",
   url = "https://www.fit.vut.cz/research/publication/8812"
}