Publication Details

Firmware Optimization for Embedded Logic Control

DVOŘÁK Václav and MIKUŠEK Petr. Firmware Optimization for Embedded Logic Control. IFAC-PapersOnLine, vol. 2009, no. 1, pp. 109-114. ISBN 978-3-902661-69-2. ISSN 1474-6670.
English title
Firmware Optimzation for Embedded Logic Control
Type
journal article
Language
czech
Authors
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT)
Mikušek Petr, Ing. (DCSY FIT BUT)
Keywords

Incompletely specified functions, multi-terminal BDDs, iterative disjunctive decomposition, firmware design, multi-way branching

Abstract

This paper presents a new method to represent a subclass of multiple-output incompletely specified functions by means of multi-terminal binary decision diagrams (MTBDDs). Algorithm to reduce the cost and width of MTBDDs is presented. A software CAD tool makes use of iterative decomposition to obtain a MTBDD data structure that can be directly mapped to firmware in a form of chained dispatch tables. On a practical example it is shown that there is a space-time trade-off between the amount of memory required for all dispatch tables in a control store and the speed of firmware execution. Support for multi-way branching in a micro-sequencer is assumed.

Published
2009
Pages
109-114
Journal
IFAC-PapersOnLine, vol. 2009, no. 1, ISSN 1474-6670
Book
4th IFAC Workshop Discrete-Event System Design
ISBN
978-3-902661-69-2
Publisher
IFAC
BibTeX 
@ARTICLE{FITPUB9074,
   author = "V\'{a}clav Dvo\v{r}\'{a}k and Petr Miku\v{s}ek",
   title = "Firmware Optimization for Embedded Logic Control",
   pages = "109--114",
   booktitle = "4th IFAC Workshop Discrete-Event System Design",
   journal = "IFAC-PapersOnLine",
   volume = 2009,
   number = 1,
   year = 2009,
   ISBN = "978-3-902661-69-2",
   ISSN = "1474-6670",
   language = "czech",
   url = "https://www.fit.vut.cz/research/publication/9074"
}
Back to top