Publication Details
Fast Cycle-Accurate Interpreted Simulation
Masařík Karel, Ing., Ph.D. (DIFS FIT BUT)
Hruška Tomáš, prof. Ing., CSc. (DIFS FIT BUT)
Husár Adam, Ing., Ph.D., MBA (RCIT FIT BUT)
Hardware/software co-design; ASIP; Architecture description language; Cycle accurate interpreted simulation; Formal models.
The area of hardware/software co-design deals with the design of ASIPs(Application Specific Instruction-set Processors) because they often create the core of an embedded system. Embedded systems with ASIPs are designed for a given task and they have to fulfill several criteria, such as power consumption, chip size, etc. The success of the design phase is closely related to the existence of good design tools, i.e. tools for ASIP programming and simulation. The simulation itself is very important, because with it we can verify and validate an ASIP design. For this purpose, ASIPs are described using an architecture description language that allows generating the design tools in an automatic way. In this article, we focus on presenting the principles which are used in our fast cycle-accurate interpreted simulator. Beside the simulation speed, we also focus on equivalence assurance between an ASIP simulator and its hardware realization.
@INPROCEEDINGS{FITPUB9181,
author = "Zden\v{e}k P\v{r}ikryl and Karel Masa\v{r}\'{i}k and Tom\'{a}\v{s} Hru\v{s}ka and Adam Hus\'{a}r",
title = "Fast Cycle-Accurate Interpreted Simulation",
pages = "9--14",
booktitle = "Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions",
year = 2009,
location = "Austin, US",
publisher = "IEEE Computer Society Press",
ISBN = "978-0-7695-4000-9",
language = "english",
url = "https://www.fit.vut.cz/research/publication/9181"
}