Publication Details
Fast Translated Simulation of ASIPs
Křoustek Jakub, Ing. (DIFS FIT BUT)
Hruška Tomáš, prof. Ing., CSc. (DIFS FIT BUT)
Kolář Dušan, doc. Dr. Ing. (DIFS FIT BUT)
Hardware/sofware co-design, Translated simulation, Architecture description language, Application-specific instruction set processors
Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One of the most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type - translated simulation - is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of this concept show very good simulation speed and fast generation of the simulator.
@INPROCEEDINGS{FITPUB9377,
author = "Zden\v{e}k P\v{r}ikryl and Jakub K\v{r}oustek and Tom\'{a}\v{s} Hru\v{s}ka and Du\v{s}an Kol\'{a}\v{r}",
title = "Fast Translated Simulation of ASIPs",
pages = "135--142",
booktitle = "6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
year = 2010,
location = "Brno, CZ",
publisher = "Masaryk University",
ISBN = "978-80-87342-10-7",
language = "english",
url = "https://www.fit.vut.cz/research/publication/9377"
}