Optimalizace aplikace testu číslicových systémů pro nízký příkon

digital circuit, test vectors, scan registers, test optimization, power consumption, power dissipation, reduction

At the beggining of the book, folowing information is presented and described in detail: basic terms related to power consumption of digital circuits, the analysis of sources of increased power consumption during the test application in comparison with normal functional mode of operation, overview of existing methods for reduction of dynamic and static power consumption during the test application. Afterwards, proposed method for simultaneous reordering of test vectors and scan registers is outlined, illustrated and described by algorithms. The method was primarily utilized to reduce dynamic part of power consumption of full scan based circuits, but it is applicable to combinatorial circuits too. For the exploration of the huge solution state space, the genetic algorithm was utilized. During the fitness computation, power consumption is evaluated by simulating a test application over the technological library. Proposed approach is able to achieve more precise results in comparison to simple methods, e.g., methods based on computation of Hamming distance between test vectors. Presented method was implemented and then tested over available sets of benchmark circuits. Results collected during the experiments as well as comparison with existing methods are presented at the end of the book.