Publication Details
SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems
Kaštil Jan, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
SEU, simulatotion, generator, framework, online testing, fault tolerance
In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.
@INPROCEEDINGS{FITPUB9585,
author = "Martin Straka and Jan Ka\v{s}til and Zden\v{e}k Kot\'{a}sek",
title = "SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems",
pages = "223--230",
booktitle = "14th EUROMICRO Conference on Digital System Design",
year = 2011,
location = "Oulu, FI",
publisher = "IEEE Computer Society",
ISBN = "978-0-7695-4494-6",
language = "english",
url = "https://www.fit.vut.cz/research/publication/9585"
}