Publication Details
Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads
FPGA, MCU, interrupt, rate, limit, overload, burst, utilization, load, adaptation
In the paper, concept and early analysis of an embedded HW/SW architecture designed to prevent the SW from interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt to various interrupt rates according to the actual MCU load. The adaptation is possible because the HW is both informed about the actual SW load on basis of signals send from the SW to the HW and able to buffer all interrupts incomming to the MCU when the SW is highly loaded or redirect the interrupts to the MCU as soon as the SW becomes underloaded.
@INPROCEEDINGS{FITPUB9644,
author = "Josef Strnadel",
title = "Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads",
pages = "21--22",
booktitle = "Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design",
year = 2011,
location = "Oulu, FI",
publisher = "Johannes Kepler University Linz",
ISBN = "978-3-902457-30-1",
language = "english",
url = "https://www.fit.vut.cz/research/publication/9644"
}