Publication Details
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
Otero Andres (UPN)
Mora Javier (UPN)
De la Torre Eduardo (UPN)
Riesgo Teresa (UPN)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)
field programmable gate array, dynamic partial reconfiguration, image filter, evolvable hardware
This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped
on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the
architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable
components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution
to a given task. Evolution of image noise filters is selected as the proof of concept application. Results show that
computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and
this can be exploited on the evolution process by using dynamic reconfiguration.
@INPROCEEDINGS{FITPUB9682, author = "Ruben Salvador and Andres Otero and Javier Mora and Eduardo Torre la De and Teresa Riesgo and Luk\'{a}\v{s} Sekanina", title = "Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support", pages = "184--191", booktitle = "Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems", year = 2011, location = "Los Alamitos, US", publisher = "IEEE Computer Society", ISBN = "978-1-4577-0599-1", language = "english", url = "https://www.fit.vut.cz/research/publication/9682" }