Publication Details

Test Platform for Fault Tolerant Systems Design Qualities Verification

STRAKA Martin, MIČULKA Lukáš, KAŠTIL Jan and KOTÁSEK Zdeněk. Test Platform for Fault Tolerant Systems Design Qualities Verification. In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012, pp. 336-341. ISBN 978-1-4673-1185-4.
Czech title
Testovací platforma pro ověřování kvality navrhu systémů odolných proti poruchám
Type
conference paper
Language
english
Authors
Straka Martin, Ing., Ph.D. (DCSY FIT BUT)
Mičulka Lukáš, Ing. (DCSY FIT BUT)
Kaštil Jan, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Keywords

controller, fault tolernat system, FPGA, SEU, injector, test platform

Abstract

In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper.

Annotation

In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper.

Published
2012
Pages
336-341
Proceedings
15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2012, Tallinn, EE
ISBN
978-1-4673-1185-4
Publisher
IEEE Computer Society
Place
Tallin, EE
BibTeX 
@INPROCEEDINGS{FITPUB9903,
   author = "Martin Straka and Luk\'{a}\v{s} Mi\v{c}ulka and Jan Ka\v{s}til and Zden\v{e}k Kot\'{a}sek",
   title = "Test Platform for Fault Tolerant Systems Design Qualities Verification",
   pages = "336--341",
   booktitle = "15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
   year = 2012,
   location = "Tallin, EE",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4673-1185-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9903"
}
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