Detail publikace

Formal Approach to RTL Testability Analysis

KOTÁSEK, Z.; RŮŽIČKA, R.; HLAVIČKA, J. Formal Approach to RTL Testability Analysis. sborník konference IEEE LATW 2000. Rio de Janeiro: unknown, 2000. p. 98-103.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kotásek Zdeněk, doc. Ing., CSc.
Růžička Richard, doc. Ing., Ph.D., MBA (UPSY)
Hlavička Jan
Klíčová slova

RTL testability analysis

Abstrakt

In the paper a formal approach to the RT level testability analysis ispresented. It is based on the structural analysis of the circuit underdesign and the classification of circuit elements. The elements areclassified on the basis of their possible role during the testapplication. The principles known from the theory of sets andmathematical logic are utilised to define the role of registers duringthe test application. The principles of developing the RT leveltestability analysis algorithms are then presented to identifyregisters for partial scan and parallel paths to apply the test of thecircuit.

Rok
2000
Strany
98–103
Sborník
sborník konference IEEE LATW 2000
Konference
IEEE LATW 2000, Rio de Janeiro, BR
Vydavatel
unknown
Místo
Rio de Janeiro
BibTeX 
@inproceedings{BUT191916,
  author="Zdeněk {Kotásek} and Richard {Růžička} and Jan {Hlavička}",
  title="Formal Approach to RTL Testability Analysis",
  booktitle="sborník konference IEEE LATW 2000",
  year="2000",
  pages="98--103",
  publisher="unknown",
  address="Rio de Janeiro"
}
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