Course details
Processor Architecture
ACH Acad. year 2010/2011 Winter semester 5 credits
The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on SIMD-style processing and vector processors. The main type of specialized processors are graphical, signal and multimedia processors. The main techniques of parallelization and pipelining of graphical and multimedia operations are explained. Basic compression techniques of graphical data are also discussed.
Guarantor
Language of instruction
Completion
Time span
- 39 hrs lectures
- 13 hrs projects
Department
Subject specific learning outcomes and competences
Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. The knowledge of architectureand hardware support of graphical and multimedia signals, their coding and compression.
Learning objectives
To familiarize students with architecture of the newest processors exploiting the instruction-level and thread-level parallelism. To clarify the role of a compiler and its cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical, signal and multimedia processors. To master basic principles of low power architectures, texture compression, mapping algorithms for multiprocessors and data flow processors.
Prerequisite knowledge and skills
Von Neumann computer architecture, memory hierarchy, microprogramming basics, programming in JSI, compiler's tasks and functions
Study literature
- aktuální PPT prezentace přednášek
- http://inst.eecs.berkeley.edu/~cs152/sp13/
- https://www.anandtech.com
- Agner Fog: Software optimization resources
- Intel Architecture Optimization Manual
- Nvidia CUDA SDK Manual
Fundamental literature
- Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1.
- Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 1136 s., ISBN 1-55860-596-7.
- Kirk, D., and Hwu, W.: Programming Massively Parallel Processors: A Hands-on Approach, Elsevier, 2010, s. 256, ISBN: 978-0-12-381472-2
- Jeffers, J., and Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming, 2013, Morgan Kaufmann, p. 432), ISBN: 978-0-124-10414-3
Syllabus of lectures
- Scalar processors. Pipelined instruction processing and instruction dependencies. Typical CPU architecture.
- Compiler-aided pipelined processing. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
- Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
- Optimization of instruction and data fetching. Examples of superscalar CPUs.
- VLIW processors. SW pipelining, predication, binary translation.
- Thread-level parallelism. Multithreaded processors, network processors.
- Data paralelism: vector processors.
- SIMD ISA extension, GPU and SIMT.
- Architecture of graphics processing units.
- Parallel computation on GPU, stream processing, OpenCL.
- Multimedia processors, Cell processor..
- Signal processors.
- Low power processors.
Progress assessment
To get 20 out of 40 points for projects and midterm examination.
Controlled instruction
Assessment of three small projects, 4 hours each, and a midterm examination.
Course inclusion in study plans
- Programme IT-MGR-2, field MBI, MIN, MIS, MMM, MSK, any year of study, Elective
- Programme IT-MGR-2, field MBS, any year of study, Compulsory-Elective
- Programme IT-MGR-2, field MGM, 2nd year of study, Elective
- Programme IT-MGR-2, field MMI, 1st year of study, Compulsory-Elective
- Programme IT-MGR-2, field MPS, MPV, 2nd year of study, Compulsory