Digital Systems Design (in English)

• 39 hrs lectures
• 13 hrs exercises

• 60 pts final exam (written part)
• 40 pts mid-term test (written part)

A practical use of selected methods for specification of combinational and sequential logic networks. An encompassment of analysis and design of simple combinational and sequential networks. An encompassment of analysis and design of simple digital equipments using combinational and sequential circuits and blocks.

To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. To learn about design of digital circuits consisting of combinational and sequential logic devices.

• Discrete Mathematics (IDM)

The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.

• Eysselt, M.: Logické systémy. Studijní opora, Učební text VUT Brno, vydáno 1980, 1985, 1990. Rozebráno: Lze si zapůjčovat v knihovnách v Brně, i na FIT.
• Frištacký, N., Kolesár, M., Kolenička, J., Hlavatý, J.: Logické systémy. SNTL Praha, ALFA Bratislava, 1986.
• Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW vydání.
• Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
• Eysselt, M.: Vybrané příklady podporující návrh číslicových systémů. Studijní opora, Učební text, FIT, 2002, 38 str. Tento text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
• Eysselt, M.: Logická a funkční schémata, výňatek z oborové normy ONT345553. Studijní opora, Učební text, FIT, 2002, 30 str. Tento text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
• Eysselt. M.: Funkční značky integrovaných obvodů, kreslení spojů. Studijní opora, Učební text, FIT, 2002, 12 str. Tento učební text zapůjčuje autor ke kopírování. Zde je WWW verze přístupná evidovaným studentům.
• Eysselt, M.: Digital Systems Design: Programmable Logic Devices. Studijní opora, Učební text, FIT VUT v Brně, 2003. Zde je WWW verze přístupná evidovaným studentům.
• McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
• Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
• Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
• Katz, R.H.: Contemporary Logic Design. Addison-Wesley/Benjamin-Cummings Publishing CO, Redwood City, CA, USA, ISBN 0-8053-2703-7, 1993.
• Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

• McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
• Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
• Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
• Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

• Binary digit system: Positional notation, conversion of base, binary codes, binary arithmetic.
• Boolean algebra, logic functions and their representations, logic expressions.
• Reduction methods: Qiune-McCluskey tabular method, Petrick's cover function.
• Reduction methods: Karnaugh maps, logic and functional diagrams.
• Analysis of logic networks behaviour: Signal races, hazards.
• Selected logic modules: Adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit.
• Sequential logic networks, latches and flip-flops.
• State machines and their representations. Design of synchronized sequential networks: State assigment, optimization and implementation. Register, counter, shift register, impulse divider.
• Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: Gate arrays, PROM, PLA, PAL.
• Simple asynchronous networks: Design, analysis of behaviour, hazards.

• Binary digit system: Positional notation, conversion of base, binary codes, binary arithmetic.
• Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
• Logic expressions. Qiune-McCluskey tabular reduction method, Petrick's cover function.
• Reduction methods: Karnaugh maps, logic and functional diagrams.
• Logic functions implementation using SSI i.cs. Behaviour analysis of logic networks: Signal races, hazards.
• Selected logic modules: Adders, subtractor.
• State machines and their representations. Design of synchronized sequential networks.
• Design of logic networks based on MSI and LSI i.cs. Programmable logic devices: Gate arrays, PROM, PLA, PAL.

• Stop and Check Test: 20 points.
• Mid-Semester Exam: 20 points.
• Final Exam: 60 points.
  Passing bounary for ECTS assessment: 50 points.

Test, mid-term exam and final exam are the monitored, and points earning, education. Test and mid-term exam are without correction eventuality. Final exam has two additional correction eventualities.

Requirements for class accreditation are not defined.