Functional Verification of Digital Systems

• 26 hrs lectures
• 8 hrs laboratories
• 18 hrs projects

• 60 pts final exam
• 20 pts labs
• 20 pts projects
• 5 pts homework

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.

A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to UVM verification methodology.

Students gain knowledge which is very valuable for their future employement, as verification is an important part of hardware development.

Digital system design, basic programming skills.

• Přednáškové materiály v elektronické formě.
• Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
• Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.
• Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
• Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.

• * Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175. * Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217 * Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141. * Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418. 

1. Motivation and history of verification
2. Simulation-based verification
3. Functional verification: introduction
4. Verification methodologies
5. Self-checking mechanisms + LAB 1
6. SystemVerilog: data types, stimuli generation + LAB 2
7. Coverage analysis + LAB 3
8. Assertions
9. Assertions-based verification + LAB 4
10. Register Abstraction Layer
11. Invited lecture
12. Validation
13. Verification trends

1. Reference model implementation.
2. Verification tests implementation.
3. Coverage-driven verification.
4. Assertions-based verification.

Design and implementation of verification environment for a selected digital systém.

Labs and project in due dates.

Requirements for class accreditation are not defined.