Course details
Diagnosis and Safe Systems
DIA Acad. year 2003/2004 Winter semester 6 credits
Fault models of TTL, CMOS, PLA and bridge faults. Test generation methods. Structural tests. Functional tests. Sequential circuit testing. RTL level test generation. Random and pseudorandom test generation. Locating sequences. Fault dictionaries. Diagnostic data compression. Design for testability, structured methods. Built-in diagnosis. Memory testing. Processor and wiring testing. Fail-safe circuits. Instrumentation for diagnosis. Verification approaches.
Guarantor
Language of instruction
Completion
Time span
Department
Subject specific learning outcomes and competences
Basic approaches to test generation and design for testability.
Learning objectives
To give the students the knowledge of methods for generation the tests for logic circuits, minimization and compression algorithms, and approaches to the design of testable circuits.
Progress assessment
Mid-term exam and a project.
Course inclusion in study plans
- Programme EI-BC-3, field VTB, 1st year of study, Elective
- Programme EI-BC-3 (in English), field VTB, 1st year of study, Elective
- Programme EI-MGR-3, field VTN, 2nd year of study, Elective
- Programme EI-MGR-5, field VTI, 2nd year of study, Elective
- Programme EI-MGR-5 (in English), field VTI, 2nd year of study, Elective