Course details
Advanced Digital Systems
PCS Acad. year 2006/2007 Winter semester 5 credits
Combinational and sequential logic design techniques, algorithms, and tools review. Structured design concept. Design strategies. Design decomposition. Design tools. Introduction to VHDL Basic features of VHDL. Simulation and synthesis. Basic VHDL modeling techniques. Algorithmic level design. Register Level Design. HDL-based design techniques. Constrained design. ASIC and PLD design process. Fast prototyping. Modeling for synthesis. Top-down design methodology in VHDL. Design case study. Design automation algorithms. HW/SW co-design.
Guarantor
Language of instruction
Completion
Time span
- 26 hrs lectures
- 10 hrs pc labs
- 16 hrs projects
Department
Subject specific learning outcomes and competences
The students are able to design complex constrained digital systems using contemporary design techniques, hardware description language VHLD, and professional CAD tools.
Learning objectives
To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.
Prerequisite knowledge and skills
Digital system design, basic programming skills.
Study literature
- Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996
Syllabus of lectures
- Combinational and sequential logic design techniques, algorithms, and tools review.
- Structured design concept. Design strategies. Design decomposition. Design tools.
- Introduction to VHDL
- Basic features of VHDL. Simulation and synthesis.
- Basic VHDL modeling techniques.
- Algorithmic level design.
- Register Level Design.
- HDL-based design techniques. Constrained design.
- ASIC and PLD design process. Fast prototyping.
- Modeling for synthesis.
- Top-down design methodology in VHDL.
- Design case study.
- Design automation algorithms. HW/SW co-design.
Syllabus of computer exercises
- Design, schematic diagram drawing, and simulation of a 4-bit full ripple-carry adder.
- Combinational logic circuits modeling and simulation using VHDL.
- Sequential logic circuits modeling and simulation using VHDL.
- A 16-bit, in VHDL described, sequential multiplier modeling, simulation, and implementation.
Progress assessment
Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.
Requirements for class accreditation are not defined.
Controlled instruction
Written mid-term exam, submitted 4 PC ab reports and project in due dates.