Thesis Details
Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru
This thesis is dealing with an option to connect the RTL simulation of a processor with a software debugger. Acording to my design, the communication between these components is handled using the JTAG and the Nexus interface. The simulation is controlled by a selected interface between hardware and software description languages. For the implementation, following components are used: JTAG adapter created by Codasip, RTL simulator Questa Advanced Simulator created by Mentor, a Siemens Business, and VPI interface for communication between Verilog and C++ languages. Concept presented in this thesis can be used on other implementations that depend on different programs and interfaces. The implementation contained in this thesis was tested and is fully functional. Nowadays, it is used by Codasip company and it will probably be updated and enhanced in the future.
JTAG interface, RTL simulation, VPI interface, Nexus interface, Codasip, Questa Advanced Simulator
Dytrych Jaroslav, Ing., Ph.D. (DCGM FIT BUT), člen
Hrubý Martin, Ing., Ph.D. (DITS FIT BUT), člen
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Švéda Miroslav, prof. Ing., CSc. (DIFS FIT BUT), člen
@bachelorsthesis{FITBT19725, author = "Kamil Michl", type = "Bachelor's thesis", title = "Lad\v{e}n\'{i} software v Codasip Studiu pomoc\'{i} JTAG rozhran\'{i} simulovan\'{e}m v RTL simul\'{a}toru", school = "Brno University of Technology, Faculty of Information Technology", year = 2017, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/19725/" }