Thesis Details
Obvodová realizace vyvíjejících se systémů
This project deals with a practical implementation of an evolvable hardware.The goal is to design and implement a complete hardware solution that utilizes areconfigurable gate array FPGA Virtex~II~Pro as a target platform.By complete hardware implementation we mean that the evolutionaryalgorithm as well as the reconfigurable circuit are implemented inhardware.The primary advantage of this approach is high speed.The proposed system will be demonstrated on task of evolutionary design ofimage operators.Evolutionary algorithm is used to find the filter which minimizes thedifference between the filtered image and desired training image.Because a complete hardware solution of this problem exists we make aneffort to design a system that gives a better performance.We decided to use a PowerPC processor integrated in FPGA which allows usimplement more efficient evolutionary algorithm in comparison to the hardwaresolution.The time-consuming evaluation part of evolutionary algorithm is running inthe hardware and the remaining part in the software.The results indicate that the proposed solution outperforms the existing solution.Furthermore, general image operators for edge detection andimpulse noise removal were discovered.
Evolutionary algorithms, Reconfigurable hardware device, Evolvable hardware, Digital filters, Hardware implementation of evolvable hardware, Hardware implementation of digital filters, Evolutionary filter design, Power PC, FPGA, Virtex II Pro
@mastersthesis{FITMT2470,
author = "Zden\v{e}k Va\v{s}\'{i}\v{c}ek",
type = "Master's thesis",
title = "Obvodov\'{a} realizace vyv\'{i}jej\'{i}c\'{i}ch se syst\'{e}m\r{u}",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2006,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/2470/"
}