Thesis Details
Implementace a verifikace vstupních a výstupních síťových bloků
Network interface blocks are basic part of the NetCOPE platform where they help to the network application designers to deal with problems of implementing the Data Link Layer of the OSI Reference Model, especially the MAC sublayer. This thesis is focused on the design and implementation of such network interface blocks operating at speed 10 Gb/s. Designed input interface block provides checking of several parts of the Ethernet frame and allows discarding of this frame based on checking results. Output interface block supports replacing frame's Source Address by a pre-set value and provides frame's CRC computation. Both network interface blocks also include a set of frames counters. Implemented network interface blocks were tested on the COMBO card. SystemVerilog verification testbench was also designed for both network interface blocks.
network interface blocks, XGMII, 10 Gigabit Ethernet, FrameLink, NetCOPE, FPGA, VHDL, SystemVerilog
Bidlo Michal, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Linhart Miroslav, doc. Ing., CSc. (DCSY FIT BUT), člen
Peringer Petr, Dr. Ing. (DITS FIT BUT), člen
@bachelorsthesis{FITBT8587,
author = "Ji\v{r}\'{i} Matou\v{s}ek",
type = "Bachelor's thesis",
title = "Implementace a verifikace vstupn\'{i}ch a v\'{y}stupn\'{i}ch s\'{i}\v{t}ov\'{y}ch blok\r{u}",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2009,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/8587/"
}